DC-Side Insulation Monitoring and Leakage Discrimination

Introduction

In photovoltaic (PV) inverter systems, the DC side is galvanically connected to the solar array and the inverter's power stage. Ensuring high insulation resistance between the DC bus and earth is critical for safety, equipment protection, and compliance with grid codes. However, measurement of insulation leakage is complicated by the presence of distributed parasitic capacitance between PV cells and the grounded frame, especially under wet or humid conditions.

This guide provides a deep dive into the algorithms used in modern inverter firmware for DC-side insulation impedance detection and leakage current monitoring. We will focus on how to distinguish between normal leakage current caused by system parasitic capacitance and dangerous leakage current due to insulation breakdown, particularly when the inverter operates in a complex grid environment with voltage disturbances and frequency deviations.

Fundamentals of DC-Side Insulation Monitoring

Insulation monitoring in a PV inverter is typically performed by injecting a low-frequency or variable-frequency signal between the DC bus and earth, or by measuring the response to a known test voltage. The most common method is the DC injection method, where a voltage source is switched across the DC bus and the leakage resistor. By measuring the resulting current or voltage divider ratio, the insulation resistance can be estimated.

In practice, the measured leakage current consists of two components: resistive leakage through insulation faults, and capacitive leakage through parasitic capacitance. The parasitic capacitance is always present, as PV modules have a large surface area and are mounted on metal frames with a thin dielectric layer. Its value can range from tens of nanofarads to several microfarads, depending on module type, rain, humidity, and the use of transformers.

Leakage Current Sources: Parasitic Capacitance vs Fault Current

Under normal operation, the total leakage current includes a capacitive charging current that changes with the common-mode voltage variation, especially when the inverter switches at high frequency. This current is not dangerous and is often called the normal leakage current. However, when insulation is damaged, a conductive path appears, creating a resistive leakage current. The challenge is that both currents are superimposed and can be similar in magnitude, especially when the parasitic capacitance is large.

An insulation fault is characterized by a low ohmic resistance (typically below 100 kΩ for a single module, or below tens of kΩ for a string ground fault) and the leakage current response is mostly resistive. In contrast, a healthy system with high parasitic capacitance presents a high impedance but with a strong phase shift. Therefore, measuring both magnitude and phase angle, or using a frequency-selective method, is essential for accurate discrimination.

Discrimination Algorithm under Complex Grid Conditions

In a complex grid environment, the inverter must withstand voltage transients, harmonics, and frequency fluctuations. These disturbances affect the leakage current measurement because they alter the common-mode voltage and induce extraneous currents. To effectively distinguish between normal parasitic leakage and real insulation damage, the algorithm should combine multiple techniques.

The first technique is adaptive thresholding. Instead of using a fixed insulation resistance threshold, the software continuously monitors the parasitic capacitance and calculates a dynamic baseline. When the grid frequency or voltage deviates, the algorithm adjusts the measurement window and uses a low-pass filter to eliminate transient peaks. This ensures that only persistent resistive leakage is treated as a fault.

Another powerful method is the use of dual-band frequency response analysis. By injecting a low-frequency signal (e.g., 0.1 Hz) and a higher-frequency signal (e.g., 1 kHz), the algorithm can separate the resistive and capacitive components. The ratio of the responses indicates the phase angle and allows precise calculation of the insulation resistance. Under grid faults, the algorithm also corroborates with the inverter's existing grid-tie protection functions, such as undervoltage and frequency ride-through, to avoid false tripping.

Practical Implementation and Calibration

For firmware engineers, implementing this discrimination algorithm begins with a robust ADC sampling strategy. The leakage current is typically sensed using a current transformer or a Hall effect sensor placed on the DC bus. The CPU synchronises sampling with the PWM carrier to reject switching noise. A software phase-locked loop (PLL) provides a reference for the grid frequency, allowing the algorithm to subtract grid-induced interference.

Calibration is equally critical. Every inverter has a parasitic capacitance signature that varies with the environment. The algorithm should include a learning phase at power-on, where the system measures the baseline capacitance