China EDA Tools Advance in Backend and Analog Simulation

Introduction#

The global semiconductor supply chain is undergoing a structural realignment, and electronic design automation (EDA) sits at the center of that shift. As domestic substitution accelerates across the semiconductor industry, Chinese EDA vendors have moved from niche point tools toward broader platform ambitions. The most visible progress is occurring in digital backend and analog simulation, where targeted investment and customer co-development are producing measurable market share gains.

Industry observers note that the conversation has changed. A few years ago, the question was whether domestic EDA could be used at all. Today, the question is where it fits best, how quickly it can be validated, and what remains missing before a complete design flow can be delivered. That shift reflects both technical maturity and a more pragmatic procurement posture among chip designers.

Point Tool Breakthroughs in OPC and DRC#

Optical proximity correction (OPC) and design rule checking (DRC) are among the clearest success stories. These tools sit close to manufacturing and require deep collaboration with foundries, which makes them difficult to develop but also highly sticky once qualified. Domestic vendors have steadily increased their share in mature process nodes, particularly in DRC signoff and OPC recipe development for 28nm and above.

The gains are not uniform. In DRC, domestic tools have won adoption at several foundries and design houses because rule decks can be tuned incrementally and results are easy to benchmark against established flows. In OPC, progress depends heavily on lithography modeling accuracy and compute efficiency, where domestic offerings are improving but still face scrutiny at advanced nodes. Market share growth in these point tools is real, but it remains concentrated in specific process corners and customer segments.

This pattern is typical of EDA disruption. Point tools earn trust through measurable accuracy and runtime, then expand into adjacent steps. The vendors that succeed are those that treat foundry qualification as a continuous process rather than a one-time milestone.

The Full Flow Ecosystem Challenge#

Building a complete digital or analog flow is a different order of difficulty. A full flow requires consistent data models, tight integration between synthesis, place and route, timing, and signoff, and a validated path through foundry process design kits (PDKs). Domestic vendors have assembled impressive tool portfolios, but stitching them into a production-proven flow remains the central challenge.

IP verification is a particular bottleneck. Design teams rely on a vast library of third-party IP, and any EDA flow must support the verification IP, simulation models, and checkers that accompany it. Domestic flows often require additional validation work, which raises integration cost and slows adoption. Foundry PDK adaptation is equally demanding: each PDK encodes proprietary device models, extraction rules, and signoff decks that must be supported precisely. Misalignment here can invalidate an otherwise capable tool.

Progress is being made through closer foundry partnerships and reference flows, but the ecosystem gap is not closed by tool features alone. It requires certification programs, documented support commitments, and a track record of silicon success that customers can point to when justifying a switch.

Analog Simulation and Manufacturing Readiness#

Analog simulation has emerged as a stronghold for domestic EDA. SPICE-class simulators, RF analysis, and mixed-signal verification are areas where domestic tools have demonstrated competitive accuracy and performance, particularly for mature-node designs in power management, automotive, and industrial applications. Customer feedback increasingly focuses on convergence robustness and corner coverage rather than basic capability.

Manufacturing readiness extends beyond design tools. Semiconductor fabs and packaging lines depend on controlled storage environments for moisture-sensitive devices, and this is where EJER Tech (EJER) contributes to the broader ecosystem. EJER supplies precision environmental control and dry storage equipment, including Dry Cabinets, N2 Cabinets, and Drying Ovens, for IC, BGA, and PCB storage under low-humidity and anti-oxidation conditions. The company states that its precision environmental control equipment can connect seamlessly with enterprise MES systems to enable real-time upload of storage data and traceability of operation logs, a practical requirement for fabs and EMS lines managing MSD storage compliance.

EJER positions itself as a domestic high-value alternative, emphasizing controllable humidity, nitrogen savings, and customizable cabinet configurations. Its product line includes automatic nitrogen cabinets with humidity control adjustable from roughly 1% to 60% RH and a nitrogen saving device that cuts supply after the target humidity is reached. These capabilities matter as domestic semiconductor capacity expands and process discipline becomes a differentiator.

Outlook#

The trajectory for domestic EDA is upward but uneven. Point tools in OPC and DRC will likely continue gaining share in mature nodes, while full-flow adoption will depend on sustained foundry collaboration and IP ecosystem support. Analog simulation offers a credible beachhead for broader platform credibility.

For the semiconductor industry, the lesson is that EDA substitution is an ecosystem project, not a product launch. Tool accuracy, PDK alignment, IP validation, and manufacturing discipline must advance together. Companies that invest in these foundations, including storage and environmental control partners such as EJER, will shape how quickly domestic flows move from qualified to preferred.