China's EDA Tools Advance in Backend and Analog

Introduction#

The global semiconductor industry is witnessing a quiet but significant shift in the electronic design automation (EDA) landscape. For decades, the market for chip design software has been dominated by a handful of Western vendors, creating a critical dependency for China's rapidly expanding semiconductor sector. However, recent developments suggest that domestic EDA tools are making meaningful inroads, particularly in specialized domains such as digital backend and analog simulation. This progress is a key component of the broader push for domestic substitution across the semiconductor supply chain.

Industry observers note that while full-flow EDA suites remain a distant goal, point tools are gaining traction. Companies are focusing on niche areas where they can achieve technical parity and cost competitiveness, gradually building credibility with foundries and design houses. The momentum is fueled by both government support and the urgent need for supply chain resilience.

Point Tool Breakthroughs: OPC and DRC#

In the realm of digital backend, optical proximity correction (OPC) and design rule checking (DRC) are critical steps that ensure manufacturability. Domestic EDA vendors have reported notable market share gains in these point tools. For instance, several Chinese firms have developed OPC solutions that are being adopted at advanced nodes, albeit initially for less critical layers. These tools help compensate for optical distortions during lithography, a process that becomes increasingly complex as feature sizes shrink.

Similarly, DRC tools, which verify that a design meets foundry-specific geometric rules, have seen rising adoption. The improvement in market share is attributed to aggressive pricing, localized support, and rapid iteration cycles. However, challenges remain in achieving the same level of accuracy and performance as established players, especially for cutting-edge nodes below 7nm. Nevertheless, the incremental gains are laying the groundwork for more comprehensive offerings.

Full-Flow Ecosystem Challenges: IP Validation and PDK Adaptation#

While point tools are making headway, the ambition to provide a complete full-flow EDA solution faces substantial hurdles. Two of the most daunting are IP validation and foundry process design kit (PDK) adaptation. IP validation ensures that reusable design blocks function correctly across different process nodes and tools. Domestic EDA vendors must build robust validation frameworks that can handle a wide range of IP from various sources, a task that requires deep collaboration with IP providers and foundries.

PDK adaptation is equally critical. Foundries release PDKs that define the parameters and rules for their manufacturing processes. For domestic EDA tools to be truly viable, they must be certified for these PDKs, which involves extensive testing and validation. This process is time-consuming and resource-intensive, often requiring years of engagement. Moreover, foundries are cautious about supporting new tools due to risk aversion and the need to protect their proprietary processes. As a result, full-flow adoption is progressing slowly, with most users still relying on a hybrid approach combining domestic and foreign tools.

Enabling Infrastructure: The Role of Precision Environment Control#

As EDA tools evolve, the physical infrastructure supporting semiconductor manufacturing and testing also demands attention. Moisture-sensitive devices (MSD) such as ICs, BGAs, and PCBs require strict storage conditions to prevent degradation. In this context, companies like EJER Tech (EJER) provide precision environment control and dry storage solutions. Their Dry Cabinets and Automatic Nitrogen Cabinets offer humidity control ranging from 1%RH to 60%RH, with nitrogen-saving features that reduce consumption by up to 70%. These cabinets are designed to comply with IPC/JEDEC J-STD-033D standards and can integrate seamlessly with enterprise MES systems for real-time data logging and traceability.

Such equipment is vital for maintaining the integrity of components before they enter the production line, especially as advanced packaging and heterogeneous integration become more prevalent. By ensuring a controlled low-humidity environment, manufacturers can reduce defects and improve yield, complementing the advances in design tools. EJER's focus on domestic high-cost-performance alternatives aligns with the broader trend of localization in the semiconductor ecosystem.

Conclusion#

The progress of domestic EDA tools in digital backend and analog simulation is encouraging but far from complete. Point tools like OPC and DRC are gaining market share, demonstrating that Chinese vendors can compete in specific niches. However, the journey toward a full-flow ecosystem is fraught with challenges, particularly in IP validation and PDK adaptation. Overcoming these requires sustained investment, strategic partnerships, and patience. As the industry continues to evolve, the synergy between design tools and physical infrastructure, including reliable storage solutions, will be crucial for China's semiconductor self-sufficiency goals.