UPF-Based Multi-Voltage Low-Power Design Flow

Introduction#

In modern integrated circuit design, low power has become one of the most important constraints together with performance, area, and reliability. A typical system-on-chip contains many intellectual property blocks that cannot all run at the same supply voltage or clock frequency. Multi-voltage design therefore requires a clear power architecture in which different power domains can operate at independent voltage levels and can be shut down or scaled dynamically.

The Unified Power Format (UPF) is an industry-standard format that lets front-end designers specify power intent at the RTL level. With UPF, the design can declare supply networks, power domains, isolation logic, level shifters, retention cells, and power switches in a reusable form. Using UPF in the front-end brings low power verification earlier, avoids late integration surprises, and enables seamless handoff to physical implementation.

Building the Power Architecture with UPF#

The first step in a multi-voltage low-power design flow is to partition the chip into power domains. A power domain is a group of logic elements that share the same supply net. In UPF, commands such as create_power_domain, create_supply_port, create_supply_net, connect_supply_net, and set_domain_supply_net are used to define the supply connections. For example, a CPU cluster can be placed in an always-on power domain, while an accelerator or graphics core can be placed in a separate switchable power domain.

Each power domain must also declare its power management cells. UPF models isolation cells, level shifters, and retention elements with commands such as set_isolation, set_level_shifter, and set_retention. Power switches can be represented by supply state definitions and a power state table that lists legal combinations of on, off, and scaled voltages. This architecture becomes the single source of truth used by synthesis, simulation, formal verification, and physical implementation tools.

From the front-end perspective, it is important to keep UPF aligned with the RTL hierarchy. If the RTL structure changes, the scope of power domains and supply connections must be updated. A robust front-end flow updates the power intent through a version control workflow and continuously verifies that every power domain has consistent isolation, level shifting, retention, and switch strategies.

Coordinating Power Gating, Multi-Vt, and DVFS#

Power gating is the dominant technique for reducing static power. A power-gated domain receives its supply through a power switch network. When the domain enters an idle state, the switch can be turned off to block the leakage path from VDD to ground. UPF associates each power domain with a switchable supply net and records the off state in its power state table. The control sequence must isolate all outputs before power is cut, retain critical state in retention flops, and then restore power with a controlled wake-up sequence.

Multi-threshold voltage optimization, or Multi-Vt, is another essential technique that can be applied during logic synthesis. Standard-cell libraries typically provide high-Vt, standard-Vt, and low-Vt implementations of the same logic functions. High-Vt cells have lower leakage but slower timing, while low-Vt cells are faster but leak more. A synthesis engine should use high-Vt cells on noncritical paths and reserve low-Vt cells for paths where timing margins are difficult. When combined with power gating, Multi-Vt reduces leakage before shutdown, while power switches further eliminate leakage in completely idle blocks.

Dynamic voltage and frequency scaling, or DVFS, reduces active power by adjusting the operating point according to workload. In a DVFS-aware power domain, the supply voltage can be raised for peak performance or lowered for energy savings, with the clock frequency following the critical-path delay. UPF describes the allowed voltage states, and level shifters are required at interfaces between domains that may be at different voltages. The real benefit emerges from coordinated strategy: Multi-Vt minimizes leakage within active and idle logic, power gating removes leakage in truly inactive domains, and DVFS trims both dynamic and static power for partially active blocks undergoing varying demand.

Low-Power Verification Checkpoints#

Low-power verification is necessary to prove that all power-management controls operate safely. Static checks should confirm that every power domain has isolation on outputs, level shifters on boundary signals crossing different voltage levels, retention cells for required state, and no missing always-on routing. The UPF supply connectivity must be checked for shorts, floating supply ports, or unintended connections between always-on and switchable supply nets.

Dynamic low-power verification exercises power-on and power-off sequences through simulation. A key checkpoint is that an isolation enable signal must be asserted before the source power domain is shut down, and it must be released only after the receiving domain sees a stable supply. The isolation and retention controls themselves must come from an always-on controller, not from logic that can be powered down. It is equally important to verify that no functional signal from an unpowered domain can propagate into an active domain without an isolation cell, and that retention save and restore operations use the correct timing window.

For DVFS domains, the simulation should include voltage transitions and frequency changes in the correct order. The clock must not change faster than the voltage can settle, and the level shifters must tolerate the intermediate voltage levels. A comprehensive regression should also compare power state table transitions against the actual UPF intent, and each transition should be evaluated for possible X-state propagation, asynchronous reset behavior, and proper sequencing among multiple power domains.

Implementation and Signoff Considerations#

The front-end low-power flow cannot stop with functional simulation. The UPF intent must be passed consistently to synthesis, clock tree synthesis, and physical design. During power plan construction, the upsized power switches and network form virtual supplies, and each macro or memory must be placed in the correct power domain. Floorplanning should consider the routing overhead of always-on supply rails, the placement of level shifters near domain boundaries, and the distance between retention controllers and isolated modules.

Signoff verification must include static timing analysis across all valid power states, including shutdown and low-voltage modes. Isolation enable and retention signals require special timing checks, and level-shifter insertion must not introduce excessive delay on high-speed paths. Finally, equivalence checking between the RTL and the post-synthesis gate-level design must be power-intent aware, using supply states to determine when two designs can be safely considered logically equivalent. By closing the loop between UPF architecture, design implementation, and verification, the team can deliver a robust multi-voltage low-power chip without signoff surprises.

Conclusion#