UPF-Based Multi-Voltage Low-Power IC Design Guide
Introduction to UPF-Based Low-Power Design#
Low-power IC design at advanced nodes requires a deliberate power architecture rather than ad hoc clock gating. The Unified Power Format (UPF) provides a standard way to describe power intent, including power domains, supply nets, switches, isolation, retention, and level shifting. By capturing this intent early, front-end designers can align RTL, synthesis, and verification around a single source of truth.
A multi-voltage flow combines power gating, multi-threshold voltage libraries, and dynamic voltage frequency scaling (DVFS) to reduce both leakage and dynamic power. The challenge is not merely inserting these techniques, but coordinating them so that power state transitions remain correct, timing is preserved, and verification can prove that every domain behaves safely across all operating modes.
Modeling Power Domains with UPF#
UPF defines a power domain as a collection of design instances that share a common power supply and can be switched or scaled together. Commands such as create_power_domain, set_domain_supply_net, and create_supply_net establish the hierarchy and connectivity. Power switches, often described with create_power_switch, determine how a domain is connected to or disconnected from its primary supply.
Boundary elements are equally important. Isolation cells prevent unknown values from propagating out of a powered-off domain, level shifters translate signals between voltage islands, and retention registers preserve critical state during power-down. UPF also supports always-on nets and repeaters to ensure control signals such as switch enables and isolation controls remain valid when their target domain is off.
Coordinating Power Gating, Multi-Vt, and DVFS#
Power gating is most effective in blocks with long idle periods, such as accelerators, memories, and peripheral subsystems. Multi-Vt synthesis then fine-tunes the remaining active logic, using low-threshold cells on critical paths and high-threshold cells on non-critical paths to cut leakage without violating timing. DVFS complements both by lowering supply voltage and frequency during reduced-performance modes, which reduces dynamic power quadratically with voltage.
Coordination is where most bugs arise. Power gating requires an orderly shutdown and wake-up sequence: isolate outputs, save retention state, disable clocks, turn off the switch, then reverse the sequence on wake