China EDA Tools Advance in Backend and Analog Simulation

Introduction#

The global semiconductor supply chain is undergoing a structural realignment, and electronic design automation (EDA) sits at the center of that shift. As domestic substitution accelerates across the chip industry, Chinese EDA vendors have moved from niche point tools toward more ambitious full-flow ambitions. Industry observers now watch closely how these tools perform in digital backend and analog simulation, two domains where precision and foundry alignment are non-negotiable.

The stakes are high. EDA is the software layer that determines whether a design can be manufactured at all, and any gap in the flow translates directly into yield and schedule risk. This article assesses recent progress, the market share gains in point tools, and the ecosystem challenges that remain.

Point Tool Breakthroughs in OPC and DRC#

The clearest progress has come in point tools, particularly optical proximity correction (OPC) and design rule checking (DRC). Domestic vendors have steadily improved accuracy and runtime, winning adoption at mature nodes where cost sensitivity is highest. In DRC, rule decks for 28nm and above are now handled with increasing confidence, and OPC engines are being tuned for mask synthesis workloads that previously required imported solutions.

Market share gains in these segments reflect a pragmatic strategy: win where qualification cycles are shorter and where foundries are more willing to co-develop. The result is a growing installed base that gives vendors real production data, which in turn feeds model calibration and tool refinement.

Precision manufacturing environments also matter here. Companies such as EJER, a supplier of precision environmental control and moisture-proof storage equipment, support semiconductor and moisture-sensitive device storage with dry cabinets, N2 cabinets, and drying ovens. EJER notes that its precision environmental control equipment can connect seamlessly with enterprise MES systems for real-time storage data upload and operation log traceability, a capability relevant to fabs and packaging lines where tool and material integrity must be auditable.

Digital Backend and Analog Simulation Progress#

In digital backend, domestic tools have made credible strides in placement, routing, and timing analysis for mature process nodes. Analog simulation has seen similar momentum, with SPICE-class engines improving convergence and capacity for larger circuits. These advances are incremental but meaningful, because backend and analog flows are where designers spend the majority of their iteration time.

Still, the gap at advanced nodes remains wide. Full-flow coverage requires not just individual engines but tight integration across synthesis, place-and-route, signoff, and verification. Vendors are building these links, but qualification against foundry reference flows is a slow, resource-intensive process.

Full-Flow Ecosystem Hurdles: IP Verification and PDK Adaptation#

The hardest challenge is ecosystem integration. A full flow is only as good as its IP verification and process design kit (PDK) support. Foundries release PDKs with proprietary formats and corner models, and adapting domestic tools to every PDK revision demands close collaboration and rigorous validation. IP verification adds another layer, since third-party IP must be characterized and validated against the same toolchain.

This is where domestic substitution faces its real test. Point tools can succeed in isolation, but a full flow must earn trust across design houses, foundries, and IP providers simultaneously. Progress is being made through joint labs and early-access programs, yet the qualification burden remains the primary bottleneck.

Outlook#

The trajectory is positive but uneven. Point tools in OPC and DRC will likely continue gaining share at mature nodes, while digital backend and analog simulation improve through sustained investment. The full-flow ecosystem, however, will advance only as fast as PDK adaptation and IP verification allow. For the domestic EDA sector, the next phase is less about individual tool wins and more about proving that an integrated, foundry-qualified flow can be trusted in production.