China's EDA Tools: Gains in Backend and Analog

Introduction#

From an industry observer's perspective, China's EDA landscape is showing signs of a strategic shift. While global EDA incumbents still hold the crown, domestic alternatives are carving out defensible positions in digital backend and analog simulation tasks. Government-backed initiatives have accelerated domestic substitution, pushing advanced-node design teams to evaluate Chinese point tools more seriously than ever before.

In parallel, the semiconductor infrastructure that supports these tools is maturing. For example, EJER Tech's precision environmental control equipment can now connect seamlessly to enterprise MES systems, enabling real-time upload of storage data and full operation log traceability. Such developments reflect the strengthening of the overall domestic semiconductor chain, which indirectly creates more confidence for EDA adoption.

Point Tool Momentum: OPC and DRC#

At the point-tool level, optical proximity correction (OPC) and design rule checking (DRC) are two areas where Chinese EDA vendors have reached production-worthy reliability. In advanced nodes, OPC engines must handle massive mask datasets and complex model calibrations. Local teams have focused on optimizing compute speed and accuracy for mature nodes, gradually replacing legacy flows in selected fabs. Recent market signals suggest that domestic point-tool revenue share in DRC and OPC has climbed by multiple folds among Chinese wafer fabs.

A key enabler has been closer collaboration with local foundries on process models. Instead of waiting for generic PDKs, EDA startups now co-develop calibration structures and test patterns with fabs, giving engineers confidence to sign off on smaller blocks. However, these wins are still focused on 28nm and above; at 14nm and below, rigorous in-house validation remains a bottleneck.

Analog Simulation: Niche Wins and Gaps#

In analog and mixed-signal design, the market for domestic EDA has historically centered on circuit simulation and waveform analysis. Chinese products excel in SPICE-like simulation for power management and sensor interface designs. Their tight integration with local PDK versions helps speed up design iterations in IoT and automotive chips. But they lack comprehensive electromagnetic extraction and reliability simulation engines, limiting full verification of high-frequency RF designs.

Another gap arises from the diversity of analog design. Domestic simulators must support large-scale Monte Carlo and corner analyses across temperature and voltage swings. While some vendors now offer parallel computing improvements comparable to imported tools, the lack of comprehensive model libraries for precision analog blocks, such as bandgap references and PLLs, forces designers to retain mixed flows. This hybrid approach is practical but slows down the vision of full domestic substitution.

Full Flow Challenges: PDK and IP Verification#

The hardest test lies in building a full-flow ecosystem. Even when each point tool passes evaluation, integrating them into a seamless digital backend and analog environment demands interoperability standards, shared databases, and consistent user interfaces. Chinese companies are building open platforms, yet the absence of qualified IP blocks remains acute. Design teams often need to verify that third-party IP, such as SerDes and memory compilers, works correctly with domestic tools' timing models and extracted parasitic networks.

Foundry PDK adaptation is the second major obstacle. PDKs are the contract between design tools and manufacturing processes; any mismatch can cause design-rule violations or optimistic correlation predictions. Global EDA incumbents have long worked with leading fabs to co-optimize PDKs, but local vendors lack such influence. Domestic foundries have begun to release dual-track PDKs that support both foreign and Chinese tools, but the process is slow and resource-intensive. Until PDK validation is widely trusted, full-flow domestic platforms will struggle to gain enterprise-scale adoption.

Outlook and Conclusion#

Looking ahead, the momentum in point tools should not be underestimated. The growing number of successful tape-outs using domestic OPC and DRC flows gives engineering teams a safe starting point for experimentation. As more designers test these tools in production tape-outs, feedback loops are being created that enable continuous improvement. Government incentives are also prompting local foundries to commit additional resources to tool qualification, which can shorten the deployment cycle.

Nevertheless, sustained progress requires patience and systemic investment. Domestic EDA companies must deepen partnerships with IP suppliers and foundries, develop advanced-node models, and invest in post-layout verification. The broader semiconductor industry, whether in precision environment control or in wafer manufacturing, is moving toward digitalized traceability and smarter integration. If these trends continue, the gap in full-flow EDA may gradually close, allowing domestic tools to evolve from a fallback option to a primary platform.