EMI Filter Design for Large Inverters to CISPR 11 Class B

Introduction#

Designing a large power inverter to meet CISPR 11 Class B limits is a complex challenge because the switching devices generate high noise levels with both differential and common mode components. The best approach combines a well-designed EMI filter with careful PCB layout. This article explains the logical steps for sizing common mode chokes and X/Y capacitors, and it describes layout techniques that suppress high-frequency coupling paths while respecting safety regulations.

Class B emission limits are much lower than Class A, so the filter design must consider the entire conducted frequency range from 150 kHz to 30 MHz. Many engineers focus only on component values, but the largest improvements come from reducing parasitic capacitance and loop inductance inside the inverter. Every filter decision must be evaluated together with the physical geometry of the power stage and the grounding strategy.

Understanding EMI Sources and Coupling Paths#

Switching transistors in the inverter create steep voltage edges that produce broadband noise. Differential mode noise travels on the phase conductors in opposite directions, while common mode interference flows on all live conductors in the same direction and returns through the protective earth or other parasitic paths. For a large inverter, common mode noise is usually dominant because the heat sink and the motor cables provide a large stray capacitance to ground.

The first step in the design is to model these coupling paths. At high frequencies, the noise current returns through the ground plane, the chassis, and any connected cable shield. If the PCB layout creates a large loop between the output switching node and the DC bus, the radiated and conducted emissions will increase. The EMI filter must present a high impedance to common mode current at the noise source and a low impedance at the AC mains boundary, but the filter itself can become a coupling path if its component placement crosses the input and output areas.

Common Mode Choke Selection and Calculation#

The common mode choke is the core element for suppressing common mode interference. It presents a high inductive impedance to common mode currents while cancelling the magnetic flux from differential mode currents. To choose the choke, estimate the required inductance L_CM from the target insertion loss. A practical formula is L_CM = V_CM / (2π f I_CM), where I_CM is the expected common mode noise current and V_CM is the noise voltage limit at the boundary. In practice, the choke impedance Z_CM must be equal to the source impedance plus the line impedance at the worst-case frequency, often around 1 MHz for large inverters.

The core material should be a high-permeability ferrite with stable impedance over the frequency band. Nano-crystalline cores yield very high permeability but can saturate under unbalanced load currents, so the safe